Job Description

Location: Santa Clara, California

Job Responsibilities:

• 8-year experience releasing complex SoC/silicon products to high volume manufacturing.
• Working knowledge of high-speed protocols like PCIe, LPDDRx, HBM, etc.
• Professional attitude with ability to execute on multiple tasks with minimal supervision.
• Strong team player with good communication skills to work alongside a team of high caliber engineers.
• Entrepreneurial, open-mind behavior and can-do attitude.

Required Experience:

• Hands-on experience with high-speed SoC test program/hardware development on Advantest 93k test platform.
• Collaboration with design DFT team to define test strategy, create and own test plan.
• Familiar with high-speed and high power load board design techniques.
• Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality.
• Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – AC/DC SCAN, MBIST, DBIst, DSerDes, DDR, D2D, DIMC and other functional tests.
• Strong knowledge of lot genealogy from 2DiD bar code down to ECID in eFuse for device serial number, chiplet Id and die information.
• Expertise in production test of high speed SerDes operating at 16Gbps and higher.
• Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug.
• Experience with lab equipment including protocol analyzers and oscilloscopes.
• Experience with data conversion between STDF file format into csv file format using scripts including extracting ECID reside with eFuse block.
• Proficiency in modern programming languages such as C/C++, Python.

Preferred Experience:

• Fluent in data processing using high level programming languages.
• Experience in running internal loopback at wafer sort as well as at FT.
• Familiarity database setup using JMP as YMS (Yield Management Tool).

Qualifications:

• BS or MS degree with Electrical/Electronic as major subjects.
• 5 – 12 years of experience.

Job Description

Location: Santa Clara, California

Job Responsibilities:

• Set up x86 SoC platforms for functional validation.
• Setting up of thermal solutions, debugger, oscilloscopes, and power measurement equipment.
• Configuring multi-boot OS with required SW, applications, tools, frameworks.
• Independently manage a group of systems to ensure stability and uninterrupted operation.
• Understand basic HW platform features – Chipset compatibility, Memory slots, expansion slots, connectivity ports, BIOS/UEFI settings.
• Basic scripting that includes modifying existing automation scripts where applicable.
• Basic understanding of different thermal solutions (e.g., air cooling, liquid cooling) and monitor temperature performance regularly – includes regular maintenance.
• Ability to configure and manage client applications on different OS environments.
• Ability to understand Client-Server workflow process and ability to analyze job logs, client logs, and test logs to identify and troubleshoot issues effectively.
• Strong troubleshooting skills to diagnose and resolve hardware, OS, and software-related issues.

Requirements:

• Familiarity with assembly and testing X86/GPU based systems.
• Familiarity in executing tests under Windows and Linux environment.
• Basic knowledge on scripting and MS Excel.
• Understanding of test and measurement equipment such as oscilloscope, DAQ and DMM.
• Experience in silicon testing environment is preferred.
• Excellent organizational and documentation skills.

Qualifications:

• B.S degree with Electrical/Electronic as major subjects.
• 5 – 10 years of experience.

Job Description

Location: Bangalore, India

Job Responsibilities:

• Set up x86 SoC platforms for functional validation.
• Setting up of thermal solutions, debugger, oscilloscopes, and power measurement equipment.
• Configuring multi-boot OS with required SW, applications, tools, frameworks.
• Independently manage a group of systems to ensure stability and uninterrupted operation.
• Understand basic HW platform features – Chipset compatibility, Memory slots, expansion slots, connectivity ports, BIOS/UEFI settings.
• Basic scripting that includes modifying existing automation scripts where applicable.
• Basic understanding of different thermal solutions (e.g., air cooling, liquid cooling) and monitor temperature performance regularly – includes regular maintenance.
• Ability to configure and manage client applications on different OS environments.
• Ability to understand Client-Server workflow process and ability to analyze job logs, client logs, and test logs to identify and troubleshoot issues effectively.
• Strong troubleshooting skills to diagnose and resolve hardware, OS, and software-related issues.

Requirements:

• Familiarity with assembly and testing X86/GPU based systems.
• Familiarity in executing tests under Windows and Linux environment.
• Basic knowledge on scripting and MS Excel.
• Understanding of test and measurement equipment such as oscilloscope, DAQ and DMM.
• Experience in silicon testing environment is preferred.
• Excellent organizational and documentation skills.

Qualifications:

• B.S degree with Electrical/Electronic as major subjects.
• 5 – 10 years of experience.

Job Description

Location: Santa Clara, California

Job Responsibilities:

• Electrical validation of different IOs (PCIe, USB3, UFS, DP, HDMI, etc.) in different chips (GPU/SOC).
• Understanding test plan.
• Setting up the DUT for different test cases - execute those test cases - record observation for each test case clearly.
• Understand spec expectation and flag in case DUT fails to meet that expectation.
• First level triage of issues/failures (like analyze and confirm that it is an actual failure and not because of some issue in board or measurement setup or other) and subsequent data collection to root-cause the failures and find out a fix.

Technical Skills - Required:

• Clarity on signal integrity concepts (e.g., insertion loss, reflections, cross talk, etc.).
• Clarity on signal quality parameters (e.g., eye diagram, jitter, frequency ppm, duty cycle, etc.) and how to measure those parameters.
• Familiarity of working in lab environment and have strong knowledge of using different equipment like DSO, Multimeter, Power supplies. (e.g., idea about ESD, minimum oscilloscope/probe BW required for measurement, etc.)
• Knowledge to understand board design from schematics (*.pdf file) and layout (*.brd file - using Cadence Allegro tool) (e.g., should be able to understand signal/power topology from schematics, should be able to locate test points in PCB for signal of interest, etc.)
• Knowledge to assemble a x86 motherboard (e.g., connect SMPS, DRAM cards, PCIe AIC, display, other peripherals, etc. to x86 motherboard).
• Knowledge of board/chip bring-up flow (e.g., idea on list of items to verify before/after attaching chip to board like verifying No-Stuff components, impedance of voltage rails, etc.)
• Proficiency in Windows & Linux OS and in Microsoft Office tools (e.g., In Linux – navigate folders, edit text files, move/copy files, SSH, execute scripts, etc.)
• Familiarity with scripting languages like Python/Perl (e.g., idea about installing different python modules, execute python scripts, etc.)

Technical Skills - Desirable:

• Knowledge and hands-on experience on high speed SERDES IO (like PCIe, USB3, UFS, Ethernet, etc.) validation (e.g., eye measurement, JTOL testing, etc.).
• Knowledge and hands-on experience of using equipment like BERT (Bit Error Ratio Tester), PCIe/USB3/UFS Logic Analyzer, etc.
• Knowledge and hands-on experience on Silicon PVT characterization.
• Knowledge and hands-on experience on board bring-up and testing.

Qualifications:

• B.E degree with Electrical/Electronic as major subjects.
• 3 – 10 years of experience.

Job Description

Location: Bangalore, India

Job Responsibilities:

• Electrical validation of different IOs (PCIe, USB3, UFS, DP, HDMI, etc.) in different chips (GPU/SOC).
• Understanding test plan.
• Setting up the DUT for different test cases - execute those test cases - record observation for each test case clearly.
• Understand spec expectation and flag in case DUT fails to meet that expectation.
• First level triage of issues/failures (like analyze and confirm that it is an actual failure and not because of some issue in board or measurement setup or other) and subsequent data collection to root-cause the failures and find out a fix.

Technical Skills - Required:

• Clarity on signal integrity concepts (e.g., insertion loss, reflections, cross talk, etc.).
• Clarity on signal quality parameters (e.g., eye diagram, jitter, frequency ppm, duty cycle, etc.) and how to measure those parameters.
• Familiarity of working in lab environment and have strong knowledge of using different equipment like DSO, Multimeter, Power supplies. (e.g., idea about ESD, minimum oscilloscope/probe BW required for measurement, etc.)
• Knowledge to understand board design from schematics (*.pdf file) and layout (*.brd file - using Cadence Allegro tool) (e.g., should be able to understand signal/power topology from schematics, should be able to locate test points in PCB for signal of interest, etc.)
• Knowledge to assemble a x86 motherboard (e.g., connect SMPS, DRAM cards, PCIe AIC, display, other peripherals, etc. to x86 motherboard).
• Knowledge of board/chip bring-up flow (e.g., idea on list of items to verify before/after attaching chip to board like verifying No-Stuff components, impedance of voltage rails, etc.)
• Proficiency in Windows & Linux OS and in Microsoft Office tools (e.g., In Linux – navigate folders, edit text files, move/copy files, SSH, execute scripts, etc.)
• Familiarity with scripting languages like Python/Perl (e.g., idea about installing different python modules, execute python scripts, etc.)

Technical Skills - Desirable:

• Knowledge and hands-on experience on high speed SERDES IO (like PCIe, USB3, UFS, Ethernet, etc.) validation (e.g., eye measurement, JTOL testing, etc.).
• Knowledge and hands-on experience of using equipment like BERT (Bit Error Ratio Tester), PCIe/USB3/UFS Logic Analyzer, etc.
• Knowledge and hands-on experience on Silicon PVT characterization.
• Knowledge and hands-on experience on board bring-up and testing.

Qualifications:

• B.E degree with Electrical/Electronic as major subjects.
• 3 – 10 years of experience.

Job Description

Location: Bangalore, India

Job Responsibilities:

• Layout Design of SRAM/CAM/RF compiler memories in 5/3FF technology.
• Development of key building blocks of memory architecture such as Row Decoder, IO, Control.
• Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing.
• Compiler level integration, verification of Compiler/Custom memories.

Skills:

• Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc.
• Good problem solving and logical reasoning skills.
• Good communication skills required.

We are looking for expertise on (Above 1 year):

• Understanding of memory architecture
• Experience in creating basic memory layouts from scratch
• Knowledge of memory peripheral blocks, including control blocks, I/O blocks, and row drivers
• Knowledge of compiler issues
• Understanding of reliability issues
• Simulation effects
• EMI (Electromagnetic Interference) considerations

Qualifications:

• Bachelor's degree or higher in Computer Science or a related field.
• 3 – 10 years of experience.

Job Description

Location: Chandler, Arizona

Job Responsibilities:

• Work as PD implementation engineer.
• Work closely with business units on Power Integrity/EMIR issues/resolve issues working with EDA vendors.
• Interface with CAD/EDA vendors on regular basis.
• Evaluate and qualify new tools/methodologies based on tool capability.
• Respond to internal business unit technical tickets, could be tool issues.
• This individual is expected to have solid experience and willing to work with key technical team in engaging with business units/CAD vendors to roll out new flow/methodology and tools.
• You will get to work with the experts who define next bleeding edge implementations.
• This role does not have any end to end PD design or working in the large ASIC/SOC project, this is stand-alone expert team guiding the different silicon development team and helping navigate issues if any.

We are looking for expertise on:

• Silicon implementation expertise
• P&R experience preferably with Cadence Innovus
• STA experience with Cadence Tempus or Synopsys Primetime
• EM/IR experience with Ansys Redhawk-SC or Cadence Voltus

Qualifications:

• Bachelor's degree or higher in Computer Science or a related field.
• 5 – 12 years of experience.

Job Description

Location: Bangalore, India

Job Responsibilities:

• Develop verification testbench components for chip/module level using SystemVerilog.
• Use high-level concepts (Object-oriented, UVM, etc) to develop an extendable environment.
• Define and execute detailed verification plan from spec working with architects and designer engineers.
• Incorporate code coverage, functional coverage, assertions, cover groups, etc to achieve 100% verification completeness before tape-out.
• Debug tests, and regression failures.
• Participate in silicon debugging and analysis.

Qualifications:

• Organized and creative thinker, motivated, and independent learner who can multitask in a dynamic environment, able to create and implement new solutions where required.
• Must be good in building verification environments preferably using the verification subset of high-level languages like System Verilog (UVM).
• Understanding or prior experience with Industry standard protocols like DDR4/DDR5 is preferred.

Education & Experience:

• MS in Computer or Electrical Engineering with a minimum of 5+ years of experience in design/verification management of highly complex projects.
• 4 – 6 years of experience.