Job Description

Location: Santa Clara, California

Job Responsibilities:

• Set up x86 SoC platforms for functional validation.
• Setting up of thermal solutions, debugger, oscilloscopes, and power measurement equipment.
• Configuring multi-boot OS with required SW, applications, tools, frameworks.
• Independently manage a group of systems to ensure stability and uninterrupted operation.
• Understand basic HW platform features – Chipset compatibility, Memory slots, expansion slots, connectivity ports, BIOS/UEFI settings.
• Basic scripting that includes modifying existing automation scripts where applicable.
• Basic understanding of different thermal solutions (e.g., air cooling, liquid cooling) and monitor temperature performance regularly – includes regular maintenance.
• Ability to configure and manage client applications on different OS environments.
• Ability to understand Client-Server workflow process and ability to analyze job logs, client logs, and test logs to identify and troubleshoot issues effectively.
• Strong troubleshooting skills to diagnose and resolve hardware, OS, and software-related issues.

Requirements:

• Familiarity with assembly and testing X86/GPU based systems.
• Familiarity in executing tests under Windows and Linux environment.
• Basic knowledge on scripting and MS Excel.
• Understanding of test and measurement equipment such as oscilloscope, DAQ and DMM.
• Experience in silicon testing environment is preferred.
• Excellent organizational and documentation skills.

Qualifications:

• B.S degree with Electrical/Electronic as major subjects.
• 5 - 10 years of experience.

Job Description

Location: Bangalore, India

Job Responsibilities:

• Interface with the engineers to define and document issues
• Consult with the senior teammates to provide guidance as necessary
• Assist in documentation of tools and flows with respect to HDL simulation and verification
• Perform tool benchmarking and testing compliance

Qualifications & Skills:

• Strong knowledge on digital circuits
• Familiar with any HDL (Verilog / VHDL)
• Exposure to Questa, Xcelium, and/or VCS is a plus
• Familiarity with Verdi, Visualizer is desirable
• Working knowledge of both Linux and Windows environments
• Ability to work effectively within a worldwide organization
• Self-motivated individual with excellent technical problem solving and debugging skills
• Strong written and verbal communication skills

Education & Experience:

• Experience: 0 - 2 years
• Educational Qualification: B.E / B.Tech / M.E / M.Tech in Electronics or related subjects

Job Description

Location: Santa Clara, California

Job Responsibilities:

• Electrical validation of different IOs (PCIe, USB3, UFS, DP, HDMI, etc.) in different chips (GPU/SOC).
• Understanding test plan.
• Setting up the DUT for different test cases - execute those test cases - record observation for each test case clearly.
• Understand spec expectation and flag in case DUT fails to meet that expectation.
• First level triage of issues/failures (like analyze and confirm that it is an actual failure and not because of some issue in board or measurement setup or other) and subsequent data collection to root-cause the failures and find out a fix.

Technical Skills - Required:

• Clarity on signal integrity concepts (e.g., insertion loss, reflections, cross talk, etc.).
• Clarity on signal quality parameters (e.g., eye diagram, jitter, frequency ppm, duty cycle, etc.) and how to measure those parameters.
• Familiarity of working in lab environment and have strong knowledge of using different equipment like DSO, Multimeter, Power supplies. (e.g., idea about ESD, minimum oscilloscope/probe BW required for measurement, etc.)
• Knowledge to understand board design from schematics (*.pdf file) and layout (*.brd file - using Cadence Allegro tool) (e.g., should be able to understand signal/power topology from schematics, should be able to locate test points in PCB for signal of interest, etc.)
• Knowledge to assemble a x86 motherboard (e.g., connect SMPS, DRAM cards, PCIe AIC, display, other peripherals, etc. to x86 motherboard).
• Knowledge of board/chip bring-up flow (e.g., idea on list of items to verify before/after attaching chip to board like verifying No-Stuff components, impedance of voltage rails, etc.)
• Proficiency in Windows & Linux OS and in Microsoft Office tools (e.g., In Linux – navigate folders, edit text files, move/copy files, SSH, execute scripts, etc.)
• Familiarity with scripting languages like Python/Perl (e.g., idea about installing different python modules, execute python scripts, etc.)

Technical Skills - Desirable:

• Knowledge and hands-on experience on high speed SERDES IO (like PCIe, USB3, UFS, Ethernet, etc.) validation (e.g., eye measurement, JTOL testing, etc.).
• Knowledge and hands-on experience of using equipment like BERT (Bit Error Ratio Tester), PCIe/USB3/UFS Logic Analyzer, etc.
• Knowledge and hands-on experience on Silicon PVT characterization.
• Knowledge and hands-on experience on board bring-up and testing.

Qualifications:

• B.E degree with Electrical/Electronic as major subjects.
• 3 - 10 years of experience.

Job Description

Location: Bangalore, India

Job Responsibilities:

• Layout Design of SRAM/CAM/RF compiler memories in 5/3FF technology.
• Development of key building blocks of memory architecture such as Row Decoder, IO, Control.
• Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing.
• Compiler level integration, verification of Compiler/Custom memories.

Skills:

• Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc.
• Good problem solving and logical reasoning skills.
• Good communication skills required.

We are looking for expertise on (Above 1 year):

• Understanding of memory architecture
• Experience in creating basic memory layouts from scratch
• Knowledge of memory peripheral blocks, including control blocks, I/O blocks, and row drivers
• Knowledge of compiler issues
• Understanding of reliability issues
• Simulation effects
• EMI (Electromagnetic Interference) considerations

Qualifications:

• Bachelor's degree or higher in Computer Science or a related field.
• 3 - 10 years of experience.

Job Description

Location: Bangalore, India

Job Responsibilities:

• Develop verification testbench components for chip/module level using SystemVerilog.
• Use high-level concepts (Object-oriented, UVM, etc) to develop an extendable environment.
• Define and execute detailed verification plan from spec working with architects and designer engineers.
• Incorporate code coverage, functional coverage, assertions, cover groups, etc to achieve 100% verification completeness before tape-out.
• Debug tests, and regression failures.
• Participate in silicon debugging and analysis.

Qualifications:

• Organized and creative thinker, motivated, and independent learner who can multitask in a dynamic environment, able to create and implement new solutions where required.
• Must be good in building verification environments preferably using the verification subset of high-level languages like System Verilog (UVM).
• Understanding or prior experience with Industry standard protocols like DDR4/DDR5 is preferred.

Education & Experience:

• MS in Computer or Electrical Engineering with a minimum of 5+ years of experience in design/verification management of highly complex projects.
• 4 - 6 years of experience.

Job Description

Location: Bangalore/Chennai/Hyderabad, India

Key Skills:

• Strong ability to read and understand legal and technical documents.
• Good at organizing and managing information in databases or spreadsheets.
• Clear writing and communication skills for creating reports and working with teams.
• Comfortable interacting with stakeholders and comparing different IP options.
• Basic knowledge of scripting or automation tools to help with data tasks.
• Attention to detail and ability to handle confidential information carefully.

Job Responsibilities:

• Read and review NDA and IP contract documents to capture important details and metadata.
• Organize and maintain IP information in databases or spreadsheets.
• Communicate with stakeholders globally to gather contract details, compare similar IPs.
• Use scripting or automation tools to make data collection and reporting easier.
• Prepare clear reports and summaries for management and other stakeholders.

Qualification:

• Bachelors or Masters in Electronics Engineering

Job Description

Location: Bangalore, India

Job Responsibilities:

• Proficiency in Layout Design and Physical Verification tools and methodologies.
• Strong understanding of Circuit Design and Analog principles.
• Experience with analog circuits and their layout techniques.
• Experience in layouts like CTLE, DFE, IDAC, PLL, LDO, BGR, TX.
• Knowledge of semiconductor design processes and industry standards.
• Attention to detail and problem-solving abilities.
• Practical experience in Serdes/DDR layout design is highly advantageous

Education & Experience:

• Bachelor's degree in Electrical Engineering, Electronics, or a related field.
• 4 - 5 years of experience on serdes/DDR layout experience. Preferably worked on TSMC 7NM, 5NM.

Job Description

Location: Shanghai, China

Job Responsibilities:

• Support post-silicon bring up, validation, and new silicon features characterization
• Support post-silicon perf/power characterization
• Set up x86 and SoC platforms for electrical and functional validation
• Execute test plan on engineering systems that involve stress testing, functional testing, power measurements, etc.
• Collect data from large number of systems, verify logs, identify failures/marginalities/outliers and report to the function owner
• Basic scripting that includes modifying existing scripts where applicable

Education & Experience:

• BS or MS in EE, CE, CS, Systems Engineering
• 2 - 3 years of meaningful PC HW experience
• Hands-on experience with silicon bring up, frequency and power characterization, Tester to System correlation, lab tools (oscilloscopes, multimeters, DAQ)
• Experienced with Windows, and Linux. Exposure to BIOS, drivers, and other software applications
• Experience with Perl, C/C++, tool and script development, Windows and Linux OS is a plus

Job Description

Location: Shanghai, China

Job Responsibilities:

• Lab management to boost up use efficiency, improve test capacity and capability
• Lab safety and security control to be compliance with company policies
• Lab PCW cooling water system support
• Support lab manager with USA/India peers to drive copy exactly in English
• Support lab manager with any other assign lab related task

Education & Experience:

• A Bachelor on Mechanical and Automation engineering is must
• Minimum of 2 years with engineering working experience
• Excellent in English communication. CET 6, TOFF certification is a plus
• Excellent on Office software tools use for data analysis and report out
• Interesting lab related work and Service spirit is a plus
• Self-motivated individual who is capable of handling multiple tasks at a time
• Service spirit with strong communication skills

Job Description

Location: Bangalore, India

Job Responsibilities:

• Architect block, cluster and top-level DV environment infrastructure
• Develop DV infrastructure from scratch
• Maintain and improve existing DV environments
• Develop test plans and tests for qualifying design at block, cluster and higher-level environments with mix of constraint random and advised stimulus
• Ensure complete verification coverage through implementation and review of code and functional coverage
• Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist
• Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up
• Support testing of design in emulation
• Lead all aspects of and manage the ASIC bring-up process

Qualifications & Experience:

• Bachelor's degree or master's Degree in equivalent experience in EE, CE, or other related field
• 7+ years of related ASIC design verification experience
• Proficient in ASIC verification using UVM/System Verilog
• Proficient in verifying sophisticated blocks, clusters and top level for ASIC
• Experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes
• Scripting experience with Perl and/or Python

Preferred Qualifications:

• Experience with Forwarding logic/Parsers/P4
• Experience with Veloce/Palladium/Zebu/HAPS
• Formal verification (iev/vc formal) knowledge
• Demonstrated ability on one or more protocols (PCIe, Ethernet, RDMA, TCP)

Job Description

Location: Bangalore, India

Job Responsibilities:

• Responsible for conducting end-to-end Signal integrity simulations for the High speed IO channels(>=112G) to meet the timing and Voltage specifications.
• Responsible for modeling of the Package and board for the channel.
• Optimization of the Package and board design for enabling the best channel margins.
• Provide inputs for the cross functional teams (Silicon, Package and Board).
• Driving the materials and connectors/cables for the platform.

Qualifications & Experience:

• More than 10 years of industry experience in Signal integrity modeling and Analysis for Package and platform.
• Prior experience working on the PCIe Gen6 or ethernet 112G interfaces.
• Strong Fundamental in transmission line theory and EM simulations tools.
• Understanding of the latest PCIE and Ethernet standards.
• Understanding of the various connector and Cable technologies (CDFP, QSFP, OSFP, Backplane, DAC, AEC, AOC).
• Experience with Signal integrity modeling and simulations tools (like ADS SI/RFPRO, HFSS).
• Experience with Signal integrity analysis tools (like ADS, HSPICE, Sigrity).
• Understanding of the Package and PCB Stack-up.

Job Description

Location: Bangalore, India

Qualifications & Experience:

• More than 10+ years of experience in the flip chip BGA package design.
• Experience working on the Large Formfactor, high layer count designs, Stack-up definition, Bump and ball map definition, Package outline drawings.
• Very good understanding of the package design rules as well as design for manufacturing and successful tape out of multiple designs.
• Knowledge of Package level signal integrity and power integrity.
• Worked on High speed Serdes (PCIE Gen6, 112-224 G Ethernet) and memory interface like DDR5, LPDDR and HBM.
• Mentor Xpedition experience is preferred.

Job Responsibilities:

• Responsible for the package design of the Leading edge AI products for Tsavorite.
• Responsible for the feasibility studies for the new IP definition and Package design concepts.
• Owning the substrate layout design from start to end and taping out multiple products.
• Co-design between Silicon, package and board.
• Collaborate closely with the Signal integrity, power integrity leads, PCB design, Mechanical and thermals to optimize the design to meet the product requirements.
• Interface with the OSAT/Packaging suppliers to understand the design rules, review the package design, meet DFM requirements and Documentation of BOM.