Job Description

Location: Bangalore, India

Job Responsibilities:

• Layout Design of SRAM/CAM/RF compiler memories in 5/3FF technology.
• Development of key building blocks of memory architecture such as Row Decoder, IO, Control.
• Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing.
• Compiler level integration, verification of Compiler/Custom memories.

Skills:

• Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc.
• Good problem solving and logical reasoning skills.
• Good communication skills required.

We are looking for expertise on (Above 1 year):

• Understanding of memory architecture
• Experience in creating basic memory layouts from scratch
• Knowledge of memory peripheral blocks, including control blocks, I/O blocks, and row drivers
• Knowledge of compiler issues
• Understanding of reliability issues
• Simulation effects
• EMI (Electromagnetic Interference) considerations

Qualifications:

• Bachelor's degree or higher in Computer Science or a related field.
• 3 - 10 years of experience.

Job Description

Location: Bangalore, India

Job Responsibilities:

• Proficiency in Layout Design and Physical Verification tools and methodologies.
• Strong understanding of Circuit Design and Analog principles.
• Experience with analog circuits and their layout techniques.
• Experience in layouts like CTLE, DFE, IDAC, PLL, LDO, BGR, TX.
• Knowledge of semiconductor design processes and industry standards.
• Attention to detail and problem-solving abilities.
• Practical experience in Serdes/DDR layout design is highly advantageous

Education & Experience:

• Bachelor's degree in Electrical Engineering, Electronics, or a related field.
• 4 - 5 years of experience on serdes/DDR layout experience. Preferably worked on TSMC 7NM, 5NM.

Job Description

Location: Shanghai, China

Job Responsibilities:

• Support post-silicon bring up, validation, and new silicon features characterization
• Support post-silicon perf/power characterization
• Set up x86 and SoC platforms for electrical and functional validation
• Execute test plan on engineering systems that involve stress testing, functional testing, power measurements, etc.
• Collect data from large number of systems, verify logs, identify failures/marginalities/outliers and report to the function owner
• Basic scripting that includes modifying existing scripts where applicable

Education & Experience:

• BS or MS in EE, CE, CS, Systems Engineering
• 2 - 3 years of meaningful PC HW experience
• Hands-on experience with silicon bring up, frequency and power characterization, Tester to System correlation, lab tools (oscilloscopes, multimeters, DAQ)
• Experienced with Windows, and Linux. Exposure to BIOS, drivers, and other software applications
• Experience with Perl, C/C++, tool and script development, Windows and Linux OS is a plus

Job Description

Location: Bangalore, India

Experience: 5–12 years

Role Overview

Skyworks is seeking a Design Verification Engineer to ensure functional correctness and robustness of mixed-signal SoC subsystems, including peripheral interfaces, audio blocks, and power management logic. You will work closely with RTL, architecture, and system teams to build comprehensive verification environments, drive coverage, and ensure first-pass silicon success.

Key Responsibilities

• Verification Architecture & Planning
  • Define and execute verification strategy for subsystems: SPI, UART, I2C, Audio interfaces (I2S, TDM), Power management digital controllers
  • Develop test plans with full functional and corner-case coverage
  • Identify verification risks and coverage gaps early
• UVM-Based Verification Development
  • Build and maintain UVM/System Verilog testbenches
  • Develop reusable VIPs and monitors, scoreboards and checkers, constrained-random stimulus
  • Implement protocol-aware verification components
• Coverage & Quality
  • Drive: functional coverage, code coverage (line, toggle, FSM)
  • Ensure closure of coverage goals and assertion checks
  • Track and report verification metrics
• Debug & Validation
  • Debug RTL issues and root-cause failures
  • Work closely with RTL engineers on bug fixes and improvements
  • Support post-silicon validation with test reuse where applicable
• System-Level Verification
  • Contribute to SoC-level verification: subsystem integration scenarios, firmware-driven tests
  • Validate interactions across clock, reset, and power domains

Required Qualifications

• 5–12 years of DV experience in SoC/subsystem verification
• Strong expertise in System Verilog and UVM
• Functional coverage and assertions (SVA)
• Experience verifying AMBA protocols (AXI/AHB/APB)
• Experience verifying peripheral interfaces (SPI, UART, I2C, I2S/TDM preferred)

Preferred Qualifications

• Experience with mixed-signal verification environments (AMS co-sim is a plus)
• Exposure to low-power verification (UPF/CPF)
• Familiarity with ARM Cortex-M33 or RISC-V SoCs

Qualification:

• Bachelor's or Master's degree in Electronics/Electrical Engineering or related field

Job Description

Location: Bangalore, India

Experience: 5–12 years

Role Overview

Skyworks is looking for a Physical Design Engineer to implement high-quality, low-power analog and digital blocks and subsystems within mixed-signal SoCs. You will be responsible for taking RTL through synthesis, place & route, and signoff, ensuring timing, power, and area targets are met. Past experience on TSMC, 22nm and below nodes. This role requires strong collaboration with RTL, DV, and analog teams to deliver silicon-ready designs.

Key Responsibilities

• Implementation Flow Ownership
  • Drive full physical design flow: Synthesis, Floorplanning, Place and route (PnR), Clock tree synthesis (CTS), Physical verification and signoff
  • Optimize for timing, power, and area (PPA)

Required Qualifications

• 5–12 years of physical design experience having worked on TSMC 22nm and below nodes
• Strong expertise in Synthesis and PnR tools (e.g., Cadence/Synopsys flows), STA and timing closure
• Experience with Advanced nodes and SoC integration, Multi-clock, multi-power domain designs

Preferred Qualifications

• Experience with mixed-signal SoC floorplanning
• Familiarity with IR drop, EM, signal integrity analysis
• Exposure to ARM Cortex-M or RISC-V based SoCs

Qualification:

• Bachelor's or Master's degree in Electronics/Electrical Engineering or related field

Job Description

Location: Bangalore, India

Qualifications & Experience:

• More than 10+ years of experience in the flip chip BGA package design.
• Experience working on the Large Formfactor, high layer count designs, Stack-up definition, Bump and ball map definition, Package outline drawings.
• Very good understanding of the package design rules as well as design for manufacturing and successful tape out of multiple designs.
• Knowledge of Package level signal integrity and power integrity.
• Worked on High speed Serdes (PCIE Gen6, 112-224 G Ethernet) and memory interface like DDR5, LPDDR and HBM.
• Mentor Xpedition experience is preferred.

Job Responsibilities:

• Responsible for the package design of the Leading edge AI products for Tsavorite.
• Responsible for the feasibility studies for the new IP definition and Package design concepts.
• Owning the substrate layout design from start to end and taping out multiple products.
• Co-design between Silicon, package and board.
• Collaborate closely with the Signal integrity, power integrity leads, PCB design, Mechanical and thermals to optimize the design to meet the product requirements.
• Interface with the OSAT/Packaging suppliers to understand the design rules, review the package design, meet DFM requirements and Documentation of BOM.

Job Description

Location: Hyderabad, India

Experience: 7–25 years

Key Responsibilities

Verification Architecture & Planning

• Define and execute verification strategy for subsystems:
  • SPI, UART, I2C
  • Audio interfaces (I2S, TDM)
  • Power management digital controllers
• Develop test plans with full functional and corner-case coverage
• Identify verification risks and coverage gaps early

UVM-Based Verification Development

• Build and maintain UVM/System Verilog testbenches
• Develop:
  • Reusable VIPs and monitors
  • Scoreboards and checkers
  • Constrained-random stimulus
• Implement protocol-aware verification components

Coverage & Quality

• Drive:
  • Functional coverage
  • Code coverage (line, toggle, FSM)
• Ensure closure of:
  • Coverage goals
  • Assertion checks
• Track and report verification metrics

Debug & Validation

• Debug RTL issues and root-cause failures
• Work closely with RTL engineers on bug fixes and improvements
• Support post-silicon validation with test reuse where applicable

System-Level Verification

• Contribute to SoC-level verification:
  • Subsystem integration scenarios
  • Firmware-driven tests
• Validate interactions across clock, reset, and power domains

Required Qualifications

• 7–25 years of DV experience in SoC/subsystem verification
• Strong expertise in:
  • System Verilog and UVM
  • Functional coverage and assertions (SVA)
• Experience verifying:
  • AMBA protocols (AXI/AHB/APB)
  • Peripheral interfaces (SPI, UART, I2C, I2S/TDM preferred)

Preferred Qualifications

• Experience with mixed-signal verification environments (AMS co-sim is a plus)
• Exposure to low-power verification (UPF/CPF)
• Familiarity with ARM Cortex-M33 or RISC-V SoCs

Qualification:

• Bachelor's or Master's degree in Electronics/Electrical Engineering or related field

Job Description

Location: Santa Clara, USA

Experience: 6–15 years

Job Description

Design Execution

• Take ownership of schematic modifications, component second sourcing, and BOM optimization for existing multi-rail, high-power PCIe accelerator cards.

DVT & Debug

• Lead the hands-on hardware bring-up and system-level debug of Corsair boards.
• Identify and resolve root causes for PCIe Gen5 link instability and power transient issues.

Power & Signal Integrity

• Execute detailed SI/PI validation plans.
• Use high-speed oscilloscopes, VNA/TDR, and BERTs to verify 32Gbps+ signals and low-voltage, high-current PDN performance.

Cross-Functional Sync

• Act as the primary technical point of contact for Thermal and Mechanical teams to resolve layout-level integration issues during the NPI (New Product Introduction) phase.

DFx Implementation

• Perform design reviews focused on DFM/DFT/DFA to ensure high-yield production readiness for upcoming manufacturing runs at Wistron.

Technical Documentation

• Generate comprehensive hardware validation reports and bring-up guides to enable seamless handoffs to the software and validation teams.

Qualification:

• Bachelor's or Master's degree in Electrical/Electronics Engineering or related field.

Job Description

Location: Santa Clara, USA

Focus: Hardware / AI Infrastructure Operations

We are seeking a highly organized and proactive Quality Engineering Contractor to support our full-time Quality and Reliability Engineering team. This is a facilitator and implementer role focused on executing Quality Management System (QMS) initiatives and managing the operational logistics of our hardware quality programs.

The Mission: You are the "Force Multiplier." Your objective is to handle the tactical implementation, documentation, and material coordination that allows the senior engineering team to focus on high-level strategy and architectural reliability.

Core Responsibilities

• QMS Implementation & Maintenance:
  • Assist FTE engineers in developing and documenting QMS processes, including Control Plans, Work Instructions, and process flows.
  • Maintain quality documentation and records to ensure audit readiness.
  • Track open action items and Corrective Actions (CAPA), ensuring no threads are lost across workstreams.
  • Support internal audits by collecting evidence and organizing findings.
• Internal RMA & Failure Analysis Support:
  • Process and track internal RMAs, maintaining accurate records of returns and dispositions.
  • Coordinate failure analysis (FA) workflows, tracking requests through closure and summarizing results.
  • Surface trends and patterns in defect data to the engineering team via regular reporting.
• Material & Logistics Coordination:
  • Coordinate physical material movement: returns, holds, quarantine, and sample management.
  • Execute cycle counts and reconcile inventory discrepancies for hardware assets, such as Units Under Test and hold inventory.
  • Liaise with Operations and Warehouse teams to ensure timely material handling.

Requirements & Qualifications

• Experience: 3–6 years in quality engineering, quality operations, or technical hardware roles.
• QMS Knowledge: Familiarity with ISO 9001 or similar quality frameworks.
• Hardware Context: Experience with PCBA or systems-level hardware environments, such as PCIe cards or server infrastructure.
• Detail Oriented: Proven ability to manage multiple open threads and maintain high data integrity.
• Communication: Strong ability to collaborate across Engineering, Operations, and Program Management.

Preferred Skills (Nice to Have)

• ASQ Certification, such as CQE or CQA.
• Familiarity with quality tools: 8D, 5-Why, and basic Statistical Process Control (SPC) concepts.
• Familiarity with PLM tools like Agile/Arena.

Job Description

Location: Bangalore

Key Responsibilities

• Own and drive DFT architecture and implementation for analog mixed signal chips from concept to production.
• Develop scan insertion, scan compression, and at-speed test strategies to meet high fault coverage and test cost targets.
• Work with cross-functional teams including design, verification, and physical design to ensure DFT integration and tapeout readiness.
• Define and implement test strategies for analog and mixed-signal IPs, including DFT hooks, wrappers, and test mode integration.
• Create test patterns and perform ATPG analysis to ensure test coverage goals are met.
• Debug DFT-related issues during silicon bring-up and collaborate with product/test engineering teams.
• Automate and optimize DFT flows and scripting for scalability and efficiency.

Required Qualifications

• B.E./B.Tech or M.E./M.Tech in Electrical/Electronics Engineering or related discipline.
• Minimum 10 years of hands-on experience in DFT with successful tapeouts.
• Strong knowledge of scan insertion, scan compression, transition fault (at-speed) testing, and boundary scan (IEEE 1149.1/1500).
• Proficiency in industry-standard DFT tools, with Cadence Modus experience highly desired.
• Experience with ATPG tools, test coverage analysis, and test pattern generation.
• Solid understanding of DFT for AMS blocks, including challenges in testability of analog circuits.
• Familiarity with scripting languages (TCL, Perl, Python) for automation.
• Good understanding of STA constraints for DFT and impact on synthesis and physical design.
• Proven experience in silicon debug and production test support.

Job Description

Location: Bangalore

Who You'll Work With

Working as part of the hardware team. Supporting hardware and software teams with various lab activities. You will also work closely with the procurement, IT and facilities team to maintain an operational lab.

What You'll Do

Lab engineers will be responsible for hardware design and test lab upkeep, procurement, maintenance, rework and bring-up support as their primary role. They will also look after AMC for equipment and calibration of test equipment. Support any internal or external lab audits.

Key Responsibilities

• Perform rework on networking products prototypes for ICs and discrete components with high quality and reliability.
• Test and troubleshoot proto boards under Hardware lead's guidance.
• Maintain well equipped and fully functional hardware rework stations at all times.
• Coordinate the Calibration and upkeep of all lab test and measurement equipment through 3rd party or OEM.
• AMC and repair for all EDVT test chambers.
• Participate in lab audits and implement any necessary corrective actions.
• Maintain inventory of all hardware test equipment, optical modules and prototypes.
• Collaborate with IT teams to implement any required security update and ensure all lab equipment with network access compliant to IT requirements.
• Co-ordinate rework activity with 3rd party lab or CM if in-house rework is not feasible.
• Procurement of lab consumables in timely manner.
• Work with logistics co-ordinator, external test partners and facilities team to ensure SEZ compliance.
• Strict adherence to safety, industry certifications, and environmental compliance regulations.

Qualifications

• Diploma in electrical, electronics or certification course in electronics and electrical repair is preferred.
• A minimum of 7 years of experience as lab technician, or lab engineer is required.
• Ability to perform complex re-work on networking hardware is a must have skill.
• Hands-on experience of using X-ray machines, BGA rework machine is a big plus, at minimum understanding of the BGA rework process is required.
• Excellent verbal and written communication is required.
• Ability to maintain clear and traceable records for inventory with web-tool is required.
• Basic understanding of networking and ability to configure network switches, Servers is needed.

Job Description

Location: Chennai

Key Responsibilities & Requirements

• Experience in Embedded firmware development.
• Experience in MISRA C, CERT C, and CWE (Common Weakness Enumeration) guidelines and making embedded firmware codebases compliant to these coding standards.
• Experience with I2C and UART is good to have.

— OR —

• Experience in Embedded firmware development with either NVMe SSD controllers (either SSD host driver or SSD device FW) or PCIe Gen4/Gen5 devices; One of these is a must.
• Experience in working with VMware ESXi environment is good to have.

Job Description

Location: Bangalore

Key Responsibilities

• Partitioning for ATPG and hierarchical approaches.
• ATPG compression and serialization.
• RTL-Scan insertion and design rule fixing.
• Expertise in Memory BIST including Memory Repair, In-System Test (IST) for Memories from Implementation to Verification and Silicon Debug.
• Experience on Boundary Scan and writing DFT mode constraints for IP's and providing the timing feedback to STA team for DFT modes.
• Experience on DFT RTL generation and Integration with RTL level QC checks like Spyglass LINT, Spyglass DFT and Fishtail.
• Familiar with IEEE1149.1, IEEE1500 and IEEE1687 standards.
• Performing ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations.
• Conducting in-depth knowledge and hands-on experience in ATPG coverage analysis.
• Working with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE.
• Being responsible for diagnostic tool generation for ATPG, MBIST, and bring-up on ATE.
• Having experience with state-of-the-art, industry-standard DFT tools.
• Being hands-on from the "nitty-gritty" details to high-level planning.

Minimum Qualifications

• BE / ME (or similar) in Electronic Engineering, Computer Science, Computer Engineering, or a related field.
• 7+ years of experience with DFT technologies, including scan test and MBIST.
• Experience with a hardware description language such as Verilog, System Verilog, or VHDL.
• Experience with one or more scripting or programming languages (e.g., Perl, Python, TCL, C, etc.).
• Ability to work well in a diverse team environment.
• Experience delivering detailed technical documentation.

Job Description

Location: Bangalore

Experience: 1 - 7 years

Job Description

Design and develop web and desktop applications using state-of-the art tools and techniques. Work with global teams and provide technical solutions to stakeholders. Participating in design discussions and code reviews.

Qualifications/Requirements

• BE or equivalent degree in Computer Science or allied branches.
• 2+ years of work experience.
• Excellent knowledge in TypeScript/JavaScript.
• Experience using React, Redux, Node.js, and web application frameworks such as Express.
• Good knowledge of Data Structures and Algorithms.
• Knowledge of Design patterns.

Job Description

Location: Santa Clara, USA

Experience: 5 - 25 years

Required Qualifications

• Bachelor's or Master's in Computer Science, Electrical Engineering, or a related field (or equivalent experience).
• 5+ years in SRE, infrastructure engineering, or systems administration.
• Strong Linux systems knowledge: networking, storage, systemd, package management, kernel parameters, and performance diagnostics.
• Hands-on experience with colocation or on-premises server infrastructure — physical hardware, rack networking, and bare-metal provisioning.
• IaC experience with Terraform and/or Ansible — writing and maintaining production configurations, not just running existing playbooks.
• Kubernetes operational experience: cluster troubleshooting, workload management, storage, and networking.
• Prometheus + Grafana or DataDog: building dashboards, writing alert rules, and understanding signal quality.
• Python and/or Bash scripting: production-quality automation, not just one-off scripts.
• Incident response experience: structured triage, RCA production, and follow-through on action items.
• Comfort operating in fast-moving startups: you own your systems, document what you build, and iterate without waiting for perfect requirements.

Strongly Preferred

• Experience operating customer-facing infrastructure or platform services with external reliability expectations.
• Cloud infrastructure operations across AWS, Azure, or GCP — including hybrid environments spanning cloud and on-prem.
• HPC job scheduler experience: Slurm, LSF, or equivalent — operations and troubleshooting.
• Knowledge of high-speed interconnect fabrics: InfiniBand, RoCE, or NVLink — configuration and troubleshooting.
• Go programming for SRE tooling — health-check services, exporters, or auto-remediation agents.
• Experience with large-scale infrastructure automation: host lifecycle management, fleet auto-healing, or AIOps-driven operations.

Job Description

Location: Santa Clara, USA

Experience: 3 - 8 years

Minimum Qualifications

• 3+ years in data center operations, hardware validation, or systems technician roles, hands-on with real servers.
• Proven rack-and-stack experience: physical server installation, PDU and patch panel cabling, rack power planning, and cable management to professional standards.
• Hardware bring-up experience: BIOS/UEFI configuration, firmware updates, component replacement, and OS installation across Linux distributions.
• Linux command-line proficiency: enough to run diagnostics, inspect logs, and execute runbooks independently.
• Asset management discipline: experience with DCIM or inventory tools and a track record of accurate, up-to-date records.
• Strong written communication: you document what you do, escalate with context, and write SOPs others can follow.
• Comfortable operating independently in a fast-moving startup environment.

Preferred Qualifications

• Prior colocation data center experience (Equinix, CoreSite, Digital Realty, or similar).
• Experience with AI/ML or GPU hardware: NVIDIA, AMD, or Intel accelerator cards in a lab or production environment.
• Basic Ansible exposure — able to run playbooks and understand what they do.
• Familiarity with high-speed interconnects: InfiniBand, RoCE, SFP/QSFP optics.
• Python or Bash scripting for operational task automation.

Job Description

Location: Bangalore

Experience: 7 - 15 years

Looking for talented Mechanical and Thermal experienced engineers.

Key Skills & Expertise

• Expertise in mechanical/thermal using industry standard tools (Solidworks, SDRC I-DEAS).
• Experience/familiarity with Pro-E, expert knowledge of SolidWorks, 2-D CAD tool AutoCad, Adobe Illustrator.
• Experience with Thermal & Fluid simulations tools such as IcePack, FloTHERM.
• Knowledge of materials & heat spreaders in datacenter, switches/routers and consumer product applications.
• Experience with standard practices and design considerations of Mechanical & Environmental Standards and to meet various telecommunication compliance requirements.
• Experience with vibration & shock testing of telecom enclosures and related solutions.
• Experience in Next-gen cooling techniques like liquid cooling, heat exchanger-based cabinets, intake air cooled cabinets, Tracking system, chassis developments in the industry, & competition (e.g. Orthogonal/Ortho Direct and EIA/ETSI racks compliant designs, approaches w.r.to "All Front Access", etc).
• Knowledge of EMI/EMC with respect to Mechanical enclosures of telecom.
• Designed and delivered wide range of systems from 1U/2U pizza-box based products to full rack, complex, high powered NEBS qualified chassis in aggressive schedules.

Job Location

UANDWE Bangalore

Education

BE/BTech/MCA

Job Description

Location: Bangalore

Experience: 8 - 15 years

Seeking Senior PCB Layout Designer who will design complex high-speed PCBs.

Key Responsibilities

• Layout for multilayer boards (>10 layers) supporting High speed Serdes Interface (upto 224G) and High-power solutions (KW).
• Create and Maintain footprints in the library and validate.
• Feasibility studies for various system and board configurations and identifying the tradeoffs.
• Perform constraint-driven routing of critical nets — length matching, differential pair tuning, via stub minimization.
• Design for DFM/DFT.

Required Qualifications

• 8+ years of professional PCB PnR experience on high-speed Serdes designs and high power.
• Deep proficiency in Altium, Cadence Allegro tool.
• Proven hands-on experience defining the HDI stack-up and designing HDI boards with blind/buried vias.
• Demonstrated expertise in symbol and footprint generation from Scratch.
• Solid understanding of SI design: Breakout, Via stubs, Loss, xtalk and impedance requirements.
• Solid understanding of PDN design: decoupling solution, Power stage and inductor design, Isolation requirements.
• B.S. in Electrical Engineering, Electronics Technology, or equivalent demonstrated experience.

Preferred Qualifications

• Worked on RF, Wireless, PCIe Gen6/7 and 112G/224G Ethernet interfaces.
• Experience having worked on Fanless designs and knowledge/experience in IP65, IP67 outdoor equipments.
• Understanding of the various connector solutions for high speed Serdes.
• Hands-on experience working from the start to the finish of the PCB design.
• Tools: Altium (must have), Cadence Allegro, Siemens Xpedition Schematic.