Job Description

Location: Santa Clara, California

Job Responsibilities:

• Set up x86 SoC platforms for functional validation.
• Setting up of thermal solutions, debugger, oscilloscopes, and power measurement equipment.
• Configuring multi-boot OS with required SW, applications, tools, frameworks.
• Independently manage a group of systems to ensure stability and uninterrupted operation.
• Understand basic HW platform features – Chipset compatibility, Memory slots, expansion slots, connectivity ports, BIOS/UEFI settings.
• Basic scripting that includes modifying existing automation scripts where applicable.
• Basic understanding of different thermal solutions (e.g., air cooling, liquid cooling) and monitor temperature performance regularly – includes regular maintenance.
• Ability to configure and manage client applications on different OS environments.
• Ability to understand Client-Server workflow process and ability to analyze job logs, client logs, and test logs to identify and troubleshoot issues effectively.
• Strong troubleshooting skills to diagnose and resolve hardware, OS, and software-related issues.

Requirements:

• Familiarity with assembly and testing X86/GPU based systems.
• Familiarity in executing tests under Windows and Linux environment.
• Basic knowledge on scripting and MS Excel.
• Understanding of test and measurement equipment such as oscilloscope, DAQ and DMM.
• Experience in silicon testing environment is preferred.
• Excellent organizational and documentation skills.

Qualifications:

• B.S degree with Electrical/Electronic as major subjects.
• 5 - 10 years of experience.

Job Description

Location: Bangalore, India

Job Responsibilities:

• Layout Design of SRAM/CAM/RF compiler memories in 5/3FF technology.
• Development of key building blocks of memory architecture such as Row Decoder, IO, Control.
• Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing.
• Compiler level integration, verification of Compiler/Custom memories.

Skills:

• Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc.
• Good problem solving and logical reasoning skills.
• Good communication skills required.

We are looking for expertise on (Above 1 year):

• Understanding of memory architecture
• Experience in creating basic memory layouts from scratch
• Knowledge of memory peripheral blocks, including control blocks, I/O blocks, and row drivers
• Knowledge of compiler issues
• Understanding of reliability issues
• Simulation effects
• EMI (Electromagnetic Interference) considerations

Qualifications:

• Bachelor's degree or higher in Computer Science or a related field.
• 3 - 10 years of experience.

Job Description

Location: Bangalore/Chennai/Hyderabad, India

Key Skills:

• Strong ability to read and understand legal and technical documents.
• Good at organizing and managing information in databases or spreadsheets.
• Clear writing and communication skills for creating reports and working with teams.
• Comfortable interacting with stakeholders and comparing different IP options.
• Basic knowledge of scripting or automation tools to help with data tasks.
• Attention to detail and ability to handle confidential information carefully.

Job Responsibilities:

• Read and review NDA and IP contract documents to capture important details and metadata.
• Organize and maintain IP information in databases or spreadsheets.
• Communicate with stakeholders globally to gather contract details, compare similar IPs.
• Use scripting or automation tools to make data collection and reporting easier.
• Prepare clear reports and summaries for management and other stakeholders.

Qualification:

• Bachelors or Masters in Electronics Engineering

Job Description

Location: Bangalore, India

Job Responsibilities:

• Proficiency in Layout Design and Physical Verification tools and methodologies.
• Strong understanding of Circuit Design and Analog principles.
• Experience with analog circuits and their layout techniques.
• Experience in layouts like CTLE, DFE, IDAC, PLL, LDO, BGR, TX.
• Knowledge of semiconductor design processes and industry standards.
• Attention to detail and problem-solving abilities.
• Practical experience in Serdes/DDR layout design is highly advantageous

Education & Experience:

• Bachelor's degree in Electrical Engineering, Electronics, or a related field.
• 4 - 5 years of experience on serdes/DDR layout experience. Preferably worked on TSMC 7NM, 5NM.

Job Description

Location: Shanghai, China

Job Responsibilities:

• Support post-silicon bring up, validation, and new silicon features characterization
• Support post-silicon perf/power characterization
• Set up x86 and SoC platforms for electrical and functional validation
• Execute test plan on engineering systems that involve stress testing, functional testing, power measurements, etc.
• Collect data from large number of systems, verify logs, identify failures/marginalities/outliers and report to the function owner
• Basic scripting that includes modifying existing scripts where applicable

Education & Experience:

• BS or MS in EE, CE, CS, Systems Engineering
• 2 - 3 years of meaningful PC HW experience
• Hands-on experience with silicon bring up, frequency and power characterization, Tester to System correlation, lab tools (oscilloscopes, multimeters, DAQ)
• Experienced with Windows, and Linux. Exposure to BIOS, drivers, and other software applications
• Experience with Perl, C/C++, tool and script development, Windows and Linux OS is a plus

Job Description

Location: Shanghai, China

Job Responsibilities:

• Lab management to boost up use efficiency, improve test capacity and capability
• Lab safety and security control to be compliance with company policies
• Lab PCW cooling water system support
• Support lab manager with USA/India peers to drive copy exactly in English
• Support lab manager with any other assign lab related task

Education & Experience:

• A Bachelor on Mechanical and Automation engineering is must
• Minimum of 2 years with engineering working experience
• Excellent in English communication. CET 6, TOFF certification is a plus
• Excellent on Office software tools use for data analysis and report out
• Interesting lab related work and Service spirit is a plus
• Self-motivated individual who is capable of handling multiple tasks at a time
• Service spirit with strong communication skills

Job Description

Location: Bangalore, India

Job Responsibilities:

• Responsible for conducting end-to-end Signal integrity simulations for the High speed IO channels(>=112G) to meet the timing and Voltage specifications.
• Responsible for modeling of the Package and board for the channel.
• Optimization of the Package and board design for enabling the best channel margins.
• Provide inputs for the cross functional teams (Silicon, Package and Board).
• Driving the materials and connectors/cables for the platform.

Qualifications & Experience:

• More than 10 years of industry experience in Signal integrity modeling and Analysis for Package and platform.
• Prior experience working on the PCIe Gen6 or ethernet 112G interfaces.
• Strong Fundamental in transmission line theory and EM simulations tools.
• Understanding of the latest PCIE and Ethernet standards.
• Understanding of the various connector and Cable technologies (CDFP, QSFP, OSFP, Backplane, DAC, AEC, AOC).
• Experience with Signal integrity modeling and simulations tools (like ADS SI/RFPRO, HFSS).
• Experience with Signal integrity analysis tools (like ADS, HSPICE, Sigrity).
• Understanding of the Package and PCB Stack-up.

Job Description

Location: Bangalore, India

Experience: 5–12 years

Role Overview

Skyworks is seeking a Design Verification Engineer to ensure functional correctness and robustness of mixed-signal SoC subsystems, including peripheral interfaces, audio blocks, and power management logic. You will work closely with RTL, architecture, and system teams to build comprehensive verification environments, drive coverage, and ensure first-pass silicon success.

Key Responsibilities

• Verification Architecture & Planning
  • Define and execute verification strategy for subsystems: SPI, UART, I2C, Audio interfaces (I2S, TDM), Power management digital controllers
  • Develop test plans with full functional and corner-case coverage
  • Identify verification risks and coverage gaps early
• UVM-Based Verification Development
  • Build and maintain UVM/System Verilog testbenches
  • Develop reusable VIPs and monitors, scoreboards and checkers, constrained-random stimulus
  • Implement protocol-aware verification components
• Coverage & Quality
  • Drive: functional coverage, code coverage (line, toggle, FSM)
  • Ensure closure of coverage goals and assertion checks
  • Track and report verification metrics
• Debug & Validation
  • Debug RTL issues and root-cause failures
  • Work closely with RTL engineers on bug fixes and improvements
  • Support post-silicon validation with test reuse where applicable
• System-Level Verification
  • Contribute to SoC-level verification: subsystem integration scenarios, firmware-driven tests
  • Validate interactions across clock, reset, and power domains

Required Qualifications

• 5–12 years of DV experience in SoC/subsystem verification
• Strong expertise in System Verilog and UVM
• Functional coverage and assertions (SVA)
• Experience verifying AMBA protocols (AXI/AHB/APB)
• Experience verifying peripheral interfaces (SPI, UART, I2C, I2S/TDM preferred)

Preferred Qualifications

• Experience with mixed-signal verification environments (AMS co-sim is a plus)
• Exposure to low-power verification (UPF/CPF)
• Familiarity with ARM Cortex-M33 or RISC-V SoCs

Qualification:

• Bachelor's or Master's degree in Electronics/Electrical Engineering or related field

Job Description

Location: Bangalore, India

Experience: 5–12 years

Role Overview

Skyworks is looking for a Physical Design Engineer to implement high-quality, low-power analog and digital blocks and subsystems within mixed-signal SoCs. You will be responsible for taking RTL through synthesis, place & route, and signoff, ensuring timing, power, and area targets are met. Past experience on TSMC, 22nm and below nodes. This role requires strong collaboration with RTL, DV, and analog teams to deliver silicon-ready designs.

Key Responsibilities

• Implementation Flow Ownership
  • Drive full physical design flow: Synthesis, Floorplanning, Place and route (PnR), Clock tree synthesis (CTS), Physical verification and signoff
  • Optimize for timing, power, and area (PPA)

Required Qualifications

• 5–12 years of physical design experience having worked on TSMC 22nm and below nodes
• Strong expertise in Synthesis and PnR tools (e.g., Cadence/Synopsys flows), STA and timing closure
• Experience with Advanced nodes and SoC integration, Multi-clock, multi-power domain designs

Preferred Qualifications

• Experience with mixed-signal SoC floorplanning
• Familiarity with IR drop, EM, signal integrity analysis
• Exposure to ARM Cortex-M or RISC-V based SoCs

Qualification:

• Bachelor's or Master's degree in Electronics/Electrical Engineering or related field

Job Description

Location: Bangalore, India

Experience: 4–10 years

Role Overview

UANDWE is looking for a skilled RTL Engineer to design and implement analog and digital subsystems for mixed-signal SoCs. You will contribute to the development of specifications for high-performance, low-power blocks including peripheral subsystem, power management (digital side of power management) based on ARM Cortex-M33 or other ARM architectures. This role offers the opportunity to work across architecture, RTL development, and SoC integration in a collaborative environment.

Key Responsibilities

• RTL Design & Development
  • Design and implement RTL for: Digital and Analog (Edge Radio) blocks
  • Serial interfaces like SPI, UART, QUAD SPI, I2C
  • Audio interfaces (I2S, TDM)
  • Power management digital blocks
  • Write clean, synthesizable, and maintainable RTL
• Specification & Micro-Architecture
  • Contribute to subsystem specifications: Functional definitions, Register maps, Interface protocols
  • Review and understand architecture documents
• Integration & Verification Support
  • Integrate RTL into SoC environment
  • Work with verification teams to: Define test scenarios, Debug functional issues, Ensure compliance with design and coding guidelines
• Debug & Analysis
  • Analyze and debug RTL and system-level issues
  • Support silicon bring-up and validation

Required Qualifications

• 4–10 years of RTL design experience
• Strong knowledge of Verilog/SystemVerilog
• Analog Radio SoC implementation, having good knowledge of Radio protocols
• Experience with at least one of: SPI, UART, I2C, I2S or TDM

Preferred Qualifications

• Experience and Exposure to ARM Cortex-M33 or other ARM cores
• Basic understanding of mixed-signal design

Qualification:

• Bachelor's or Master's degree in Electronics/Electrical Engineering or related field

Job Description

Location: Bangalore, India

Experience: 10–15+ years

Role Overview

UANDWE is looking for a skilled RTL Lead to design and implement analog and digital subsystems for mixed-signal SoCs. You will contribute to the development of specifications for high-performance, low-power blocks including peripheral subsystem, power management (digital side of power management) based on ARM Cortex-M33 or other ARM architectures. This role offers the opportunity to work across architecture, RTL development, and SoC integration in a collaborative environment.

Key Responsibilities

• RTL Design & Development
  • Design and implement RTL for: Digital and Analog (Edge Radio) blocks
  • Serial interfaces like SPI, UART, QUAD SPI, I2C
  • Audio interfaces (I2S, TDM)
  • Power management digital blocks
  • Write clean, synthesizable, and maintainable RTL
  • Lead and guide junior RTL engineers on the team
• Specification & Micro-Architecture
  • Contribute to subsystem specifications: Functional definitions, Register maps, Interface protocols
  • Review and understand architecture documents
  • Own micro-architecture documentation for complex blocks
• Integration & Verification Support
  • Integrate RTL into SoC environment
  • Work with verification teams to: Define test scenarios, Debug functional issues, Ensure compliance with design and coding guidelines
  • Review verification plans and coverage reports
• Debug & Analysis
  • Analyze and debug RTL and system-level issues
  • Support silicon bring-up and validation
  • Drive root-cause analysis for complex failures

Required Qualifications

• 10–15+ years of RTL design experience
• Strong knowledge of Verilog/SystemVerilog
• Analog Radio SoC implementation, having good knowledge of Radio protocols
• Experience with at least one of: SPI, UART, I2C, I2S or TDM
• Proven experience leading technical teams or mentoring junior engineers

Preferred Qualifications

• Experience and Exposure to ARM Cortex-M33 or other ARM cores
• Basic understanding of mixed-signal design
• Experience with low-power design techniques (clock gating, power gating, UPF)
• Familiarity with synthesis and timing constraints

Qualification:

• Bachelor's or Master's degree in Electronics/Electrical Engineering or related field

Job Description

Location: Bangalore, India

Qualifications & Experience:

• More than 10+ years of experience in the flip chip BGA package design.
• Experience working on the Large Formfactor, high layer count designs, Stack-up definition, Bump and ball map definition, Package outline drawings.
• Very good understanding of the package design rules as well as design for manufacturing and successful tape out of multiple designs.
• Knowledge of Package level signal integrity and power integrity.
• Worked on High speed Serdes (PCIE Gen6, 112-224 G Ethernet) and memory interface like DDR5, LPDDR and HBM.
• Mentor Xpedition experience is preferred.

Job Responsibilities:

• Responsible for the package design of the Leading edge AI products for Tsavorite.
• Responsible for the feasibility studies for the new IP definition and Package design concepts.
• Owning the substrate layout design from start to end and taping out multiple products.
• Co-design between Silicon, package and board.
• Collaborate closely with the Signal integrity, power integrity leads, PCB design, Mechanical and thermals to optimize the design to meet the product requirements.
• Interface with the OSAT/Packaging suppliers to understand the design rules, review the package design, meet DFM requirements and Documentation of BOM.

Job Description

Location: Chandler, US or Chennai, India

Experience: 5–8 years

Job Description

CAD team is looking for highly analytical and detail-oriented Application Engineer, having an understanding on ASIC Design and building blocks used in such a design. This role involves capturing and managing IP metadata, comparing IP offerings, and collaborating with business unit leaders to gather IP information. They would need to review Non-Disclosure Agreements (NDAs) and Intellectual Property (IP) contract documents. Scripting knowledge is an added advantage for automating data extraction and reporting processes.

Key Skills

• Strong knowledge on ASIC Design flow and IPs that get used in chip design.
• Strong ability to read and understand legal and technical documents.
• Good at organizing and managing information in databases or spreadsheets.
• Clear writing and communication skills for working with remote teams / customers.
• Comfortable interacting with stakeholders and comparing different IP options.
• Basic knowledge of scripting or automation tools to help with data tasks.
• Attention to detail and ability to handle confidential information carefully.

Job Responsibilities

• Organize and maintain IP information in databases or spreadsheets.
• Communicate with stakeholders globally to gather contract details, compare similar IPs.
• Read and review NDA and IP contract documents to capture important details and metadata.
• Use scripting or automation tools to make data collection and reporting easier.
• Prepare clear reports and summaries for management and other stakeholders.

Qualification

• Bachelors or Masters in Electronics Engineering with 5-8 years of experience

Job Description

Location: Bangalore, India

Experience: 2+ years

Core Job Responsibilities

• Administer and maintain the PLM system including item master, BOMs, documents, and workflows
• Manage Engineering Change Orders (ECOs), Deviation Requests, and Change Notices across hardware product lines
• Collaborate with team members from operations (MFG, test) and partner teams (mechanical, electrical, and firmware teams) to ensure accurate and up-to-date product data
• Support NPI (New Product Introduction) processes and manage product structure setup
• Maintain integrations between PLM and ERP systems to ensure data consistency across manufacturing and supply chain
• Generate and analyze PLM reports to support product and program management decisions
• Identify process gaps and recommend improvements to PLM workflows and governance standards

Qualifications

• Bachelor's degree in engineering, manufacturing, supply chain, or a related technical field
• 2+ years of experience as a PLM analyst, configuration management analyst, or similar role in a hardware or electronics company
• Hands-on experience with at least one PLM platform (e.g., Teamcenter, Windchill, Agile, Arena)
• Strong understanding of BOM structures, part numbering, change management, and document control
• Familiarity with ERP systems (SAP, Oracle, NetSuite) and PLM-ERP integration concepts
• Excellent communication skills to work cross-functionally with engineering, operations, and quality teams
• Strong analytical skills and attention to detail for managing complex product data

Nice to Have

• Arena PLM
• Experience with CAD data management and ECAD/MCAD integrations
• Familiarity with RoHS, REACH, or other regulatory compliance tracking within PLM

Job Description

Location: Bangalore, India

Experience: 5–15 years

Role Overview:

In this role, you will be responsible for Gate-Level Simulation (GLS) verification of complex SoCs across IP, subsystem, and full-chip levels. The focus will be on validating timing correctness, reset/power behavior, clock-domain crossings, and ensuring functional equivalence between RTL and gate-level implementations. The task list includes, but is not limited to, GLS testplan development, environment adaptation, SDF back-annotation, regression execution, and debug of timing and initialization issues at various design hierarchies.

Roles And Responsibilities:

• Partner with RTL Design, Synthesis, and Physical Design teams to understand timing constraints, clocking architecture, reset strategy, and low-power intent.
• Develop comprehensive GLS test plans covering timing scenarios, reset/initialization sequences, power-aware behavior, and corner-case conditions across IP, subsystem, and chip levels.
• Adapt and enhance existing RTL verification environments for gate-level simulations, including handling X-propagation, timing checks, and initialization differences.
• Perform SDF back-annotation and validate setup/hold timing, clock skew, and multi-cycle/false path behavior.
• Execute GLS regressions (zero-delay, unit-delay, full-timing) and analyze failures related to timing violations, metastability, and unknown (X) propagation.
• Debug complex GLS issues including race conditions, reset sequencing problems, clock-domain crossing (CDC) issues, and mismatches between RTL and netlist behavior.
• Validate low-power features such as clock gating, power gating, retention, and isolation in gate-level environments.
• Perform equivalence-oriented validation between RTL and gate-level simulations and support signoff readiness.
• Collaborate with DFT teams to validate scan insertion, ATPG patterns, and test modes in gate-level environments.
• Support post-silicon bring-up by correlating GLS results with silicon behavior and debugging initialization/timing-related issues.
• Track and communicate DV progress using metrics such as GLS coverage, regression status, bug tracking, and closure reports.

Requirements:

• Bachelor's or Master's degree in Electrical/Electronics Engineering/Computer Engineering/Science with 5 to 15 years of relevant experience
• Strong understanding of digital design fundamentals, timing concepts (setup/hold, clock skew, jitter), and static timing analysis (STA)
• Proven expertise in Gate-Level Simulation (GLS) including SDF back-annotation, timing simulation modes, and debug of timing-related issues
• Strong knowledge of clock-domain crossing (CDC), reset-domain crossing (RDC), and metastability concepts
• Hands-on experience with SystemVerilog/UVM and/or C/C++ based verification methodologies
• Experience with industry-standard simulation and debug tools (Questa, Visualizer)
• Familiarity with constrained-random verification, assertions, and functional/code coverage methodologies

Preferred Qualifications:

• Experience in adapting RTL UVM environments for GLS with focus on X-propagation handling and timing awareness
• Hands-on expertise in GLS across IP, subsystem, and full-chip levels for complex SoCs
• Familiarity with low-power verification methodologies (UPF/CPF), including retention, isolation, and power state transitions
• Experience working with synthesis and STA tools (e.g., PrimeTime) and understanding of timing closure flows
• Exposure to DFT/scan/ATPG validation and test mode verification in GLS
• Experience with scripting and automation for GLS regression management (Python/Perl/Shell)
• Understanding of equivalence checking concepts and flows (RTL vs gate-level)
• Strong debugging skills for complex gate-level issues and ability to drive closure across cross-functional teams
• Strong drive for DV infrastructure automation and signoff quality improvements

Qualification:

• Bachelor's or Master's degree in Electrical/Electronics Engineering/Computer Engineering/Science or related field

Job Description

Location: Bangalore, India

Experience: 5–15 years

Role Overview:

In this role, you will be working on high-performance GPU cores and graphics subsystems at block and SoC levels. The responsibilities include verification of GPU IP in both standalone and integrated environments, ensuring functional correctness, performance validation, and interoperability across system components. The task list includes, but is not limited to, testplan development, environment development, checker/scoreboard creation, test execution, and debug at IP, subsystem, and SoC levels.

Roles And Responsibilities:

• Partner with Architects and RTL Design teams to understand GPU architecture, graphics pipeline, and system-level requirements.
• Formulate comprehensive test and coverage plans aligned with GPU architecture and micro-architecture (compute, graphics, memory hierarchy, and interconnect).
• Develop verification environments with reusable components such as BFMs, drivers, monitors, scoreboards, assertions, and coverage models.
• Build and integrate GPU-specific verification components including traffic generators, shader/compute workload generators, and memory models.
• Create verification plans and develop testbenches tailored to GPU IP blocks (e.g., shader cores, command processor, memory subsystem) and full GPU subsystem integration.
• Execute verification plans including design bring-up, DV environment setup, regression execution, feature validation, and debug of complex functional and performance issues.
• Perform integration verification of GPU IP with system interconnects (AXI/NoC), memory subsystems (DDR/HBM), cache hierarchies, and power/clock domains.
• Validate graphics and compute workloads, scheduling, coherency, bandwidth utilization, and corner-case scenarios.
• Support post-silicon bring-up, validation, and debug activities, including correlation with pre-silicon results.
• Track and communicate DV progress using key metrics such as testplan status, bug tracking, and functional/code coverage.

Requirements:

• Bachelor's or Master's degree in Electrical/Electronics Engineering/Computer Engineering/Science with 5 to 15 years of relevant experience
• Strong architecture knowledge of GPU design, including graphics pipeline and memory subsystems
• Strong expertise in System Verilog/UVM methodology and/or C/C++ based verification with 5+ years of hands-on experience in IP/subsystem/SoC level verification
• Hands-on experience with industry-standard simulation and debug tools (Questa, Visualizer)
• Experience with constrained-random verification, functional coverage, and assertion-based verification methodologies

Preferred Qualifications:

• Experience in developing UVM-based verification environments from scratch for complex GPU or high-performance compute IPs
• Hands-on expertise in GPU IP verification
• Strong knowledge of AMBA protocols (AXI/AHB/APB) and NoC-based system integration
• Experience with performance verification, profiling, and bottleneck analysis in GPU subsystems
• Experience with cache coherency, virtualization, and multi-core/multi-engine GPU systems
• Exposure to post-silicon validation, lab bring-up, and debug

Qualification:

• Bachelor's or Master's degree in Electrical/Electronics Engineering/Computer Engineering/Science or related field

Job Description

Location: Bangalore, India

Experience: 5–15 years

Role Overview:

In this role, you will be working on high-speed USB controllers (USB 3.x, USB4) and subsystem integration at block and SoC levels. The responsibilities include verification of USB IP in standalone and integrated environments, ensuring compliance with protocol specifications, and validating interoperability across different system components. The task list includes, but is not limited to, testplan development, environment development, checker/scoreboard creation, test execution, and debug at IP, subsystem, and SoC levels.

Roles And Responsibilities:

• Partner with Architects and RTL Design teams to understand USB architecture, integration requirements, and system-level use cases.
• Develop comprehensive test plans and coverage models aligned with USB specifications and micro-architecture (USB 3.x, USB4).
• Build and enhance verification environments using reusable components such as BFMs, drivers, monitors, scoreboards, assertions, and protocol checkers.
• Develop and integrate USB VIPs, host/device models, and system-level components for end-to-end verification.
• Create verification plans and develop testbenches tailored to USB IP, subsystem integration, and SoC-level validation.
• Execute verification plans including design bring-up, environment setup, regression execution, feature validation, and debug of complex protocol and integration issues.
• Perform integration verification of USB IP with interconnects (AXI/AHB/APB), PHY/SerDes, power management, and other SoC components.
• Validate USB protocol compliance, link training, enumeration, power states, and error handling scenarios.
• Support post-silicon bring-up, validation, and debug activities including lab correlation with pre-silicon results.
• Track and communicate DV progress using metrics such as testplan completion, bug tracking, and functional/code coverage.

Requirements:

• Bachelor's or Master's degree in Electrical/Electronics Engineering/Computer Engineering/Science with 5 to 15 years of relevant experience
• Strong architecture and protocol knowledge in USB standards (USB 3.x, USB4), including link, transaction, and power management layers
• Good understanding of USB PHY/SerDes interfaces, PIPE interface, and high-speed signaling basics
• Strong expertise in System Verilog/UVM methodology and/or C/C++ based verification with 5+ years of hands-on experience in IP/subsystem/SoC level verification
• Hands-on experience with industry-standard simulation and debug tools (Questa, VCS, Verdi/Visualizer)
• Experience with constrained-random verification, functional coverage, and assertion-based verification methodologies

Preferred Qualifications:

• Experience developing UVM-based verification environments from scratch for complex IPs
• Hands-on expertise in USB controller verification in host, device, and OTG/dual-role modes
• Experience with USB compliance testing, interoperability testing, and certification requirements
• Familiarity with industry-standard USB VIPs (e.g. Avery) and building protocol-specific stimulus
• Strong knowledge of AMBA protocols (AXI/AHB/APB) and their integration with USB subsystems
• Experience with low-power verification (power states, clock gating, retention) in USB subsystems
• Exposure to post-silicon validation, lab bring-up, and debugging using analyzers/protocol tools

Qualification:

• Bachelor's or Master's degree in Electrical/Electronics Engineering/Computer Engineering/Science or related field

Job Description

Location: Bangalore, India

Experience: 10+ years

Role Overview:

Seeking Senior PCB Layout Designer who will support the physical design of complex, high-speed PCBs.

Key Responsibilities:

• Layout for multilayer boards (>10 layers) supporting High speed Serdes Interface (up to 224G) and High power solutions (KW)
• Create and maintain footprints in the library and validate
• Feasibility studies for various system and board configurations and identifying the tradeoffs
• Perform constraint-driven routing of critical nets — length matching, differential pair tuning, via stub minimization
• Design for DFM/DFT

Required Qualifications:

• 10+ years of professional PCB layout experience on high-speed Serdes designs and high power
• Deep proficiency in Cadence Allegro tool
• Proven hands-on experience defining the HDI stack-up and designing HDI boards with blind/buried vias
• Demonstrated expertise in symbol and footprint generation from Scratch
• Solid understanding of SI design: Breakout, Via stubs, Loss, xtalk and impedance requirements
• Solid understanding of PDN design: decoupling solution, Power stage and inductor design, Isolation requirements
• B.S. in Electrical Engineering, Electronics Technology, or equivalent demonstrated experience

Preferred Qualifications:

• Worked on PCIe Gen6/7 and 112G/224G Ethernet interfaces
• Understanding of the various connector solutions for high speed Serdes
• Hands-on experience working from the start to the finish of the PCB design

Tools:

• Cadence Allegro, Siemens Xpedition Schematic

Qualification:

• Bachelor's degree in Electrical Engineering, Electronics Technology, or equivalent demonstrated experience